Properties In Electronic Design Automation

ABSTRACT

One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property&#39;s value is not dependent upon the value of any other properties. Alternately, a property may be a compound property, where the definition of the property&#39;s value incorporates another, previously-determined property value. Still further, a property may be an alternative property, where the property is assigned one value definition under a first set of conditions and assigned another value definition under a second set of conditions. A first electronic design automation process may generate one or more property values. The generated property values then can be passed to another electronic design automation process in the design analysis flow for its use.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 60/850,716 entitled “Properties In Electronic Design Automation,”filed on Oct. 9, 2006, and naming Fedor Pikus as inventor, whichapplication is incorporated entirely herein by reference.

FIELD OF THE INVENTION

The present invention is directed to the use of properties in electronicdesign automation. Various implementations of the invention may beuseful for exchanging one or more properties between processes in anautomated electronic design tool.

BACKGROUND OF THE INVENTION

Many microdevices, such as integrated circuits, have become so complexthat these devices cannot be manually designed. For example, even asimple microprocessor may have millions and millions of transistors thatcooperate to form the components of the microprocessor. As a result,electronic design automation tools have been created to assist circuitdesigners in analyzing a circuit design before it is manufactured. Theseelectronic design automation tools typically will execute one or moreelectronic design automation (EDA) processes to verify that the circuitdesign complies with specified requirements, identify problems in thedesign, modify the circuit design to improve its manufacturability, orsome combination thereof. For example, some electronic design automationtools may provide one or more processes for simulating the operation ofa circuit manufactured from a circuit design to verify that the designwill provides the desired functionality. Still other electronic designautomation tools may alternately or additionally provide one or moreprocesses for confirming that a circuit design matches the intendedcircuit schematic, for identifying portions of a circuit design that donot comply with preferred design conventions, for identifying flaws orother weaknesses the design, or for modifying the circuit design toaddress any of these issues. Examples of electronic design automationtools include the Calibre family of software tools available from MentorGraphics Corporation of Wilsonville, Oreg.

As electronic design automation tools continue to develop, greatersophistication is being demanded from these tools. For example, inaddition to detecting obvious design flaws, many electronic designautomation tools are now expected to identify those design objects in adesign that have a significant likelihood of being improperly formedduring the manufacturing process, determine the resultant impact onmanufacturing yield that these design objects will create, and/oridentify design changes that will allow the design objects to be morereliably manufactured during the manufacturing process (e.g.,“design-for-manufacture” (DFM)). In order to meet these expectations, aprocess executed by an electronic design automation tool may need toperform more calculations than with previous generations of electronicdesign automation tools. For example, a design rule check process mayconfirm that the polygons used in a physical layout design to formindividual wiring lines are separated by a minimum specified distance.In addition, however, the design rule check process also may determinethe likelihood that the polygons may nonetheless form the wiring lineswith an erroneous bridging fault. This determination may require, forexample, calculating the distance between the polygons, the length forwhich the polygons run adjacent to each other, and the thickness of thepolygons at their adjacent portions.

Because even a single process executed by an electronic designautomation tool may require millions of calculations, improvements inthe speed and efficiency of electronic design automation tools arecontinuously being sought. Still further, additional functionality forelectronic design automation tools also is continuously being sought, inorder to improve their usefulness to circuit designers andmanufacturers.

BRIEF SUMMARY OF THE INVENTION

Aspects of the invention relate to techniques of more efficientlyprocessing data for electronic design automation. As will be discussedin detail below, embodiments of both tools and methods implementingthese techniques have particular application for analyzing microdevicedesign data, such as integrated circuit design data.

According to various implementations of the invention, one or moreproperties can be associated with a design object in a microdevicedesign. The design object may be any data in a physical layout designfor a microdevice. For example, the design object may be a geometricelement in a layout design, such as a polygon, a polygon edge, a groupof edges, or one or more vertices of a polygon. The design object alsomay be a collection of geometric elements in a layout design, such as agroup of polygons, a cell in a hierarchical design, every cell of aspecified type in a hierarchical design, or even a collection of all ofthe geometric elements in a layer of a design. Still further, the designobject may be any item of data in another type of circuit design,including a non-geometric item, such as a net, device, or instance of aconnection pin in a logical circuit design for an integrated circuit, orthe placement of a cell in a hierarchical circuit design.

With some examples of the invention, one or more properties may bestatically assigned during the execution of a design process by anelectronic design automation tool. Alternately or additionally, one ormore properties may be dynamically generated during the execution of adesign process by an electronic design automation tool. A property mayhave any desired data value. For example, a property may be assigned aconstant value or a vector value. Alternately, a property may beassigned a variable value. For example, a property may be defined by anequation or other type of script that includes one or more variables. Aproperty's value thus may be dynamically derived from, e.g., geometricdata in the design.

A property may be a simple property, where the definition of theproperty's value is not dependent upon the value of any otherproperties. Alternately, a property may be a compound property, wherethe definition of the property's value incorporates one or more other,previously-determined property values. Still further, a property may bean alternative property. With an alternative property, the property willhave one value definition under a first set of conditions, and anothervalue definition under a second set of conditions.

A property also may have multiple values. A property may have, forexample, an x-coordinate value, a y-coordinate value, and a z-coordinatevalue. Moreover, a property may have multiple, heterogeneous values. Forexample, a property may have both a numerical value and a string value.A property associated with a cell in a hierarchical layout circuitdesign thus could have a numerical value that may be, e.g., a devicecount of devices in the cell, and a string value that may be, e.g., amodel name identifying the library source for the cell. Of course, aproperty with multiple heterogeneous values can have any combination oftypes of value definitions, including any combination of the types ofvalue definitions described above (e.g., one or more constant valuedefinitions, one or more vector value definitions, one or more dynamicvalue definitions, one or more simple value definitions, one or morecompound value definitions, one or more string value definitions, etc.).A property may even have multiple alternative value definitions, whereone or more of the alternative value definitions are of different types.

Advantageously, various implementations of the invention may allow afirst electronic design automation process to generate one or moreproperty values. The generated property values can then be passed toanother electronic design automation process. For example, a design rulecheck (DRC) process may generate one or more property values for each ofa plurality of geometric elements in a physical layout design. Thedesign rule check process can then pass these property values onto asecond electronic design automation process, such as an opticalproximity correction (OPC) process. By using the property valuesprovided by the design rule check process, the optical proximitycorrection process can avoid having to recalculate the property values.This use of property values may be particularly beneficial where thesecond electronic design automation process cannot easily calculate theproperty values itself, or where the second electronic design automationprocess cannot calculate the property values as quickly or efficientlyas the first electronic design automation process.

Similarly, property values may be generated by a first portion of anelectronic design automation process, and subsequently provided to asecond portion of the same electronic design process. For example, oneportion of a design-for-manufacture (DFM) process may generate a set ofproperty values for each of a plurality of geometric elements in aphysical layout design during a first operation. The first portion ofthe design-for-manufacture process can then provide the calculatedproperties to a second, subsequent portion of the process. This use ofproperty values may be particularly beneficial where the second portionof the electronic design automation process cannot easily calculate theproperty values itself, or where the second portion of the electronicdesign automation process cannot calculate the property values asquickly or efficiently as the first portion of the electronic designautomation process.

These and other features and aspects of the invention will be apparentupon consideration of the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a computing system that may be used toimplement various embodiments of the invention.

FIG. 2 illustrates an example of a multi-core processor unit that may beused to implement various embodiments of the invention.

FIG. 3 schematically illustrates an example of a family of softwaretools for automatic design automation that may employ associativeproperties according to various embodiments of the invention.

FIG. 4 illustrates geometric elements in a microcircuit layout designthat may be associated with one or more properties according to variousembodiments of the invention.

FIG. 5 illustrates one example of a type of array that may be employedby various embodiments of the invention.

FIG. 6 illustrates a flowchart showing a method that an EDA process mayuse to generate and provide a property value to another EDA process.

FIG. 7 illustrates a flowchart showing a method that a first portion ofan EDA process may use to generate and provide a property value to asecond portion of an EDA process.

DETAILED DESCRIPTION OF THE INVENTION Exemplary Operating Environment

The execution of various electronic design automation processesaccording to embodiments of the invention may be implemented usingcomputer-executable software instructions executed by one or moreprogrammable computing devices. Because these embodiments of theinvention may be implemented using software instructions, the componentsand operation of a generic programmable computer system on which variousembodiments of the invention may be employed will first be described.Further, because of the complexity of some electronic design automationprocesses and the large size of many circuit designs, various electronicdesign automation tools are configured to operate on a computing systemcapable of simultaneously running multiple processing threads. Thecomponents and operation of a computer network having a host or mastercomputer and one or more remote or servant computers therefore will bedescribed with reference to FIG. 1. This operating environment is onlyone example of a suitable operating environment, however, and is notintended to suggest any limitation as to the scope of use orfunctionality of the invention.

In FIG. 1, the computer network 101 includes a master computer 103. Inthe illustrated example, the master computer 103 is a multi-processorcomputer that includes a plurality of input and output devices 105 and amemory 107. The input and output devices 105 may include any device forreceiving input data from or providing output data to a user. The inputdevices may include, for example, a keyboard, microphone, scanner orpointing device for receiving input from a user. The output devices maythen include a display monitor, speaker, printer or tactile feedbackdevice. These devices and their connections are well known in the art,and thus will not be discussed at length here.

The memory 107 may similarly be implemented using any combination ofcomputer readable media that can be accessed by the master computer 103.The computer readable media may include, for example, microcircuitmemory devices such as read-write memory (RAM), read-only memory (ROM),electronically erasable and programmable read-only memory (EEPROM) orflash memory microcircuit devices, CD-ROM disks, digital video disks(DVD), or other optical storage devices. The computer readable media mayalso include magnetic cassettes, magnetic tapes, magnetic disks or othermagnetic storage devices, punched media, holographic storage devices, orany other medium that can be used to store desired information.

As will be discussed in detail below, the master computer 103 runs asoftware application for performing one or more operations according tovarious examples of the invention. Accordingly, the memory 107 storessoftware instructions 109A that, when executed, will implement asoftware application for performing one or more operations. The memory107 also stores data 109B to be used with the software application. Inthe illustrated embodiment, the data 109B contains process data that thesoftware application uses to perform the operations, at least some ofwhich may be parallel.

The master computer 103 also includes a plurality of processor units 111and an interface device 113. The processor units 111 may be any type ofprocessor device that can be programmed to execute the softwareinstructions 109A, but will conventionally be a microprocessor device.For example, one or more of the processor units 111 may be acommercially generic programmable microprocessor, such as Intel®Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™microprocessors or Motorola 68K/Coldfire® microprocessors. Alternatelyor additionally, one or more of the processor units 111 may be acustom-manufactured processor, such as a microprocessor designed tooptimally perform specific types of mathematical operations. Theinterface device 113, the processor units 111, the memory 107 and theinput/output devices 105 are connected together by a bus 115.

With some implementations of the invention, the master computing device103 may employ one or more processing units 111 having more than oneprocessor core. Accordingly, FIG. 2 illustrates an example of amulti-core processor unit 111 that may be employed with variousembodiments of the invention. As seen in this figure, the processor unit111 includes a plurality of processor cores 201. Each processor core 201includes a computing engine 203 and a memory cache 205. As known tothose of ordinary skill in the art, a computing engine contains logicdevices for performing various computing functions, such as fetchingsoftware instructions and then performing the actions specified in thefetched instructions. These actions may include, for example, adding,subtracting, multiplying, and comparing numbers, performing logicaloperations such as AND, OR, NOR and XOR, and retrieving data. Eachcomputing engine 203 may then use its corresponding memory cache 205 toquickly store and retrieve data and/or instructions for execution.

Each processor core 201 is connected to an interconnect 207. Theparticular construction of the interconnect 207 may vary depending uponthe architecture of the processor unit 201. With some processor cores201, such as the Cell microprocessor created by Sony Corporation,Toshiba Corporation and IBM Corporation, the interconnect 207 may beimplemented as an interconnect bus. With other processor units 201,however, such as the Opteron™ and Athlon™ dual-core processors availablefrom Advanced Micro Devices of Sunnyvale, Calif., the interconnect 207may be implemented as a system request interface device. In any case,the processor cores 201 communicate through the interconnect 207 with aninput/output interface 209 and a memory controller 211. The input/outputinterface 209 provides a communication interface between the processorunit 201 and the bus 115. Similarly, the memory controller 211 controlsthe exchange of information between the processor unit 201 and thesystem memory 107. With some implementations of the invention, theprocessor units 201 may include additional components, such as ahigh-level cache memory accessible shared by the processor cores 201.

While FIG. 2 shows one illustration of a processor unit 201 that may beemployed by some embodiments of the invention, it should be appreciatedthat this illustration is representative only, and is not intended to belimiting. For example, some embodiments of the invention may employ amaster computer 103 with one or more Cell processors. The Cell processoremploys multiple input/output interfaces 209 and multiple memorycontrollers 211. Also, the Cell processor has nine different processorcores 201 of different types. More particularly, it has six or moresynergistic processor elements (SPEs) and a power processor element(PPE). Each synergistic processor element has a vector-type computingengine 203 with 428×428 bit registers, four single-precision floatingpoint computational units, four integer computational units, and a 556KB local store memory that stores both instructions and data. The powerprocessor element then controls that tasks performed by the synergisticprocessor elements. Because of its configuration, the Cell processor canperform some mathematical operations, such as the calculation of fastFourier transforms (FFTs), at substantially higher speeds than manyconventional processors.

It also should be appreciated that, with some implementations, amulti-core processor unit 111 can be used in lieu of multiple, separateprocessor units 111. For example, rather than employing six separateprocessor units 111, an alternate implementation of the invention mayemploy a single processor unit 111 having six cores, two multi-coreprocessor units each having three cores, a multi-core processor unit 111with four cores together with two separate single-core processor units111, etc.

Returning now to FIG. 1, the interface device 113 allows the mastercomputer 103 to communicate with the servant computers 117A, 117B, 117C. . . 117 x through a communication interface. The communicationinterface may be any suitable type of interface including, for example,a conventional wired network connection or an optically transmissivewired network connection. The communication interface may also be awireless connection, such as a wireless optical connection, a radiofrequency connection, an infrared connection, or even an acousticconnection. The interface device 113 translates data and control signalsfrom the master computer 103 and each of the servant computers 117 intonetwork messages according to one or more communication protocols, suchas the transmission control protocol (TCP), the user datagram protocol(UDP), and the Internet protocol (IP). These and other conventionalcommunication protocols are well known in the art, and thus will not bediscussed here in more detail.

Each servant computer 117 may include a memory 119, a processor unit121, an interface device 123, and, optionally, one more input/outputdevices 125 connected together by a system bus 127. As with the mastercomputer 103, the optional input/output devices 125 for the servantcomputers 117 may include any conventional input or output devices, suchas keyboards, pointing devices, microphones, display monitors, speakers,and printers. Similarly, the processor units 121 may be any type ofconventional or custom-manufactured programmable processor device. Forexample, one or more of the processor units 121 may be commerciallygeneric programmable microprocessors, such as Intel® Pentium® or Xeon™microprocessors, Advanced Micro Devices Athlon™ microprocessors orMotorola 68K/Coldfire® microprocessors. Alternately, one or more of theprocessor units 121 may be custom-manufactured processors, such asmicroprocessors designed to optimally perform specific types ofmathematical operations. Still further, one or more of the processorunits 121 may have more than one core, as described with reference toFIG. 2 above. For example, with some implementations of the invention,one or more of the processor units 121 may be a Cell processor. Thememory 119 then may be implemented using any combination of the computerreadable media discussed above. Like the interface device 113, theinterface devices 123 allow the servant computers 117 to communicatewith the master computer 103 over the communication interface.

In the illustrated example, the master computer 103 is a multi-processorunit computer with multiple processor units 111, while each servantcomputer 117 has a single processor unit 121. It should be noted,however, that alternate implementations of the invention may employ amaster computer having single processor unit 111. Further, one or moreof the servant computers 117 may have multiple processor units 121,depending upon their intended use, as previously discussed. Also, whileonly a single interface device 113 or 123 is illustrated for both themaster computer 103 and the servant computers, it should be noted that,with alternate embodiments of the invention, either the computer 103,one or more of the servant computers 117, or some combination of bothmay use two or more different interface devices 113 or 123 forcommunicating over multiple communication interfaces.

With various examples of the invention, the master computer 103 may beconnected to one or more external data storage devices. These externaldata storage devices may be implemented using any combination ofcomputer readable media that can be accessed by the master computer 103.The computer readable media may include, for example, microcircuitmemory devices such as read-write memory (RAM), read-only memory (ROM),electronically erasable and programmable read-only memory (EEPROM) orflash memory microcircuit devices, CD-ROM disks, digital video disks(DVD), or other optical storage devices. The computer readable media mayalso include magnetic cassettes, magnetic tapes, magnetic disks or othermagnetic storage devices, punched media, holographic storage devices, orany other medium that can be used to store desired information.According to some implementations of the invention, one or more of theservant computers 117 may alternately or additionally be connected toone or more external data storage devices. Typically, these externaldata storage devices will include data storage devices that also areconnected to the master computer 103, but they also may be differentfrom any data storage devices accessible by the master computer 103.

It also should be appreciated that the description of the computernetwork illustrated in FIG. 1 and FIG. 2 is provided as an example only,and it not intended to suggest any limitation as to the scope of use orfunctionality of alternate embodiments of the invention.

Electronic Design Automation

As previously noted, various embodiments of the invention are related toelectronic design automation. In particular, various implementations ofthe invention may be used to improve the operation of electronic designautomation software tools that identify, verify and/or modify designdata for manufacturing a microdevice, such as a microcircuit. As usedherein, the terms “design” and “design data” are intended to encompassdata describing an entire microdevice, such as an integrated circuitdevice or micro-electromechanical system (MEMS) device. This term alsois intended to encompass a smaller set of data describing one or morecomponents of an entire microdevice, however, such as a layer of anintegrated circuit device, or even a portion of a layer of an integratedcircuit device. Still further, the terms “design” and “design data” alsoare intended to encompass data describing more than one microdevice,such as data to be used to create a mask or reticle for simultaneouslyforming multiple microdevices on a single wafer. It should be notedthat, unless otherwise specified, the term “design” as used herein isintended to encompass any type of design, including both a physicallayout design and a logical design.

Designing and fabricating microcircuit devices involve many steps duringa ‘design flow’ process. These steps are highly dependent on the type ofmicrocircuit, its complexity, the design team, and the fabricator orfoundry that will manufacture the microcircuit from the design. Severalsteps are common to most design flows, however. First, a designspecification is modeled logically, typically in a hardware designlanguage (HDL). Once a logical design has been created, various logicalanalysis processes are performed on the design to verify itscorrectness. More particularly, software and hardware “tools” verifythat the logical design will provide the desired functionality atvarious stages of the design flow by running software simulators and/orhardware emulators, and errors are corrected. For example, a designermay employ one or more functional logic verification processes to verifythat, given a specified input, the devices in a logical design willperform in the desired manner and provide the appropriate output.

In addition to verifying that the devices in a logic design will providethe desired functionality, some designers may employ a design logicverification process to verify that the logical design meets specifieddesign requirements. For example, a designer may create rules such as,e.g., every transistor gate in the design must have an electrical pathto ground that passes through no more than three other devices, or everytransistor that connects to a specified power supply also must beconnected to a corresponding ground node, and not to any other groundnode. A design logic verification process then will determine if alogical design complies with specified rules, and identify occurrenceswhere it does not.

After the logical design is deemed satisfactory, it is converted intophysical design data by synthesis software. This physical design data or“layout” design data may represent, for example, the geometric elementsthat will be written onto a mask used to fabricate the desiredmicrocircuit device in a photolithographic process at a foundry. Forconventional mask or reticle writing tools, the geometric elementstypically will be polygons of various shapes. Thus, the layout designdata usually includes polygon data describing the features of polygonsin the design. It is very important that the physical design informationaccurately embody the design specification and logical design for properoperation of the device. Accordingly, after it has been created during asynthesis process, the physical design data is compared with theoriginal logical design schematic in a process sometimes referred to asa “layout-versus-schematic” (LVS) process.

Once the correctness of the logical design has been verified, andgeometric data corresponding to the logical design has been created in alayout design, the geometric data then may be analyzed. For example,because the physical design data is employed to create masks used at afoundry, the data must conform to the foundry's requirements. Eachfoundry specifies its own physical design parameters for compliance withtheir processes, equipment, and techniques. Accordingly, the design flowmay include a process to confirm that the design data complies with thespecified parameters. During this process, the physical layout of thecircuit design is compared with design rules in a process commonlyreferred to as a “design rule check” (DRC) process. In addition to rulesspecified by the foundry, the design rule check process may also checkthe physical layout of the circuit design against other design rules,such as those obtained from test chips, general knowledge in theindustry, previous manufacturing experience, etc.

With modern electronic design automation design flows, a designer mayadditionally employ one or more “design-for-manufacture” (DFM) softwaretools. As previously noted, design rule check processes attempt toidentify, e.g., elements representing structures that will almostcertainly be improperly formed during a manufacturing process.“Design-For-Manufacture” tools, however, provide processes that attemptto identify elements in a design representing structures with asignificant likelihood of being improperly formed during themanufacturing process. A “design-for-manufacture” process mayadditionally determine what impact the improper formation of theidentified elements will have on the yield of devices manufactured fromthe circuit design, and/or modifications that will reduce the likelihoodthat the identified elements will be improperly formed during themanufacturing process. For example, a “design-for-manufacture” (DFM)software tool may identify wires that are connected by only a singlevia, determine the yield impact for manufacturing a circuit from thedesign based upon the probability that each individual single via willbe improperly formed during the manufacturing process, and then identifyareas where redundant vias can be formed to supplement the single vias.

It should be noted that, in addition to “design-for-manufacture,”various alternate terms are used in the electronic design automationindustry. Accordingly, as used herein, the term “design-for-manufacture”or “design-for-manufacturing” is intended to encompass any electronicdesign automation process that identifies elements in a designrepresenting structures that may be improperly formed during themanufacturing process. Thus, “design-for-manufacture” (DFM) softwaretools will include, for example, “lithographic friendly design” (LFD)tools that assist designers to make trade-off decisions on how to createa circuit design that is more robust and less sensitive to lithographicprocess windows. They will also include “design-for-yield” (DFY)electronic design automation tools, “yield assistance” electronic designautomation tools, and “chip cleaning” and “design cleaning” electronicdesign automation tools.

After a designer has used one or more geometry analysis processes toverify that the physical layout of the circuit design is satisfactory,the designer may then perform one or more simulation processes tosimulate the operation of a manufacturing process, in order to determinehow the design will actually be realized by that particularmanufacturing process. A simulation analysis process may additionallymodify the design to address any problems identified by the simulation.For example, some design flows may employ one or more processes tosimulate the image formed by the physical layout of the circuit designduring a photolithographic process, and then modify the layout design toimprove the resolution of the image that it will produce during aphotolithography process.

These resolution enhancement techniques (RET) may include, for example,modifying the physical layout using optical proximity correction (OPC)or by the addition of sub-resolution assist features (SRAF). Othersimulation analysis processes may include, for example, phase shift mask(PSM) simulation analysis processes, etch simulation analysis processesand planarization simulation analysis processes. Etch simulationanalysis processes simulate the removal of materials during a chemicaletching process, while planarization simulation processes simulate thepolishing of the circuit's surface during a chemical-mechanical etchingprocess. These simulation analysis processes may identify, for example,regions where an etch or polishing process will not leave a sufficientlyplanar surface. These simulation analysis processes may then modify thephysical layout design to, e.g., include more geometric elements inthose regions to increase their density.

Once a physical layout design has been finalized, the geometric elementsin the design are formatted for use by a mask or reticle writing tool.Masks and reticles typically are made using tools that expose a blankreticle or mask substrate to an electron or laser beam (or to an arrayof electron beams or laser beams), but most mask writing tools are ableto only “write” certain kinds of polygons, however, such as righttriangles, rectangles or other trapezoids. Moreover, the sizes of thepolygons are limited physically by the maximum beam (or beam array) sizeavailable to the tool. Accordingly, the larger geometric elements in aphysical layout design data will typically be “fractured” into thesmaller, more basic polygons that can be written by the mask or reticlewriting tool.

It should be appreciated that various design flows may repeat one ormore processes in any desired order. Thus, with some design flows,geometric analysis processes can be interleaved with simulation analysisprocesses and/or logical analysis processes. For example, once thephysical layout of the circuit design has been modified using resolutionenhancement techniques, then a design rule check process ordesign-for-manufacturing process may be performed on the modifiedlayout, Further, these processes may be alternately repeated until adesired degree of resolution for the design is obtained. Similarly, adesign rule check process and/or a design-for-manufacturing process maybe employed after an optical proximity correction process, a phase shiftmask simulation analysis process, an etch simulation analysis process ora planarization simulation analysis process. Examples of electronicdesign tools that employ one or more of the logical analysis processes,geometry analysis processes or simulation analysis processes discussedabove are described in U.S. Pat. No. 6,230,299 to McSherry et al.,issued May 8, 2001, U.S. Pat. No. 6,249,903 to McSherry et al., issuedJun. 19, 2001, U.S. Pat. No. 6,339,836 to Eisenhofer et al., issued Jan.15, 2002, U.S. Pat. No. 6,397,372 to Bozkus et al., issued May 28, 2002,U.S. Pat. No. 6,415,421 to Anderson et al., issued Jul. 2, 2002, andU.S. Pat. No. 6,425,113 to Anderson et al., issued Jul. 23, 2002, eachof which are incorporated entirely herein by reference.

Software Tools for Simulation, Verification or Modification of a CircuitLayout

To facilitate an understanding of various embodiments of the invention,one such software tool for automatic design automation, directed to theanalysis and modification of a design for an integrated circuit, willnow be generally described. As previously noted, the terms “design” and“design data” are used herein to encompass data describing an entiremicrodevice, such as an integrated circuit device ormicro-electromechanical system (MEMS) device. These terms also areintended, however, to encompass a smaller set of data describing one ormore components of an entire microdevice, such as a layer of anintegrated circuit device, or even a portion of a layer of an integratedcircuit device. Still further, the terms “design” and “design data” alsoare intended to encompass data describing more than one microdevice,such as data to be used to create a mask or reticle for simultaneouslyforming multiple microdevices on a single wafer. As also previouslynoted, unless otherwise specified, the term “design” as used herein isintended to encompass any type of design, including both physical layoutdesigns and logical designs.

As seen in FIG. 3, an analysis tool 301, which may be implemented by avariety of different software applications, includes a data importmodule 303 and a hierarchical database 305. The analysis tool 301 alsoincludes a layout-versus-schematic (LVS) verification module 307, adesign rule check (DRC) module 309, a design-for-manufacturing (DFM)module 311, an optical proximity correction (OPC) module 313, and anoptical proximity rule check (ORC) module 315. The analysis tool 301 mayfurther include other modules 317 for performing additional functions asdesired, such as a phase shift mask (PSM) module (not shown), an etchsimulation analysis module (not shown) and/or a planarization simulationanalysis module (not shown). The tool 301 also has a data export module319. One example of such an analysis tool is the Calibre family ofsoftware applications available from Mentor Graphics Corporation ofWilsonville, Oreg.

Initially, the tool 301 receives data 321 describing a physical layoutdesign for an integrated circuit. The layout design data 321 may be inany desired format, such as, for example, the Graphic Data System II(GDSII) data format or the Open Artwork System Interchange Standard(OASIS) data format proposed by Semiconductor Equipment and MaterialsInternational (SEMI). Other formats for the data 321 may include an opensource format named Open Access, Milkyway by Synopsys, Inc., and EDDM byMentor Graphics, Inc. The layout data 321 includes geometric elementsfor manufacturing one or more portions of an integrated circuit device.For example, the initial integrated circuit layout data 321 may includea first set of polygons for creating a photolithographic mask that inturn will be used to form an isolation region of a transistor, a secondset of polygons for creating a photolithographic mask that in turn willbe used to form a contact electrode for the transistor, and a third setof polygons for creating a photolithographic mask that in turn will beused to form an interconnection line to the contact electrode. Theinitial integrated circuit layout data 321 may be converted by the dataimport module 303 into a format that can be more efficiently processedby the remaining components of the tool 301.

Once the data import module 303 has converted the original integratedcircuit layout data 321 to the appropriate format, the layout data 321is stored in the hierarchical database 305 for use by the variousoperations executed by the modules 305-317. Next, thelayout-versus-schematic module 307 checks the layout design data 321 ina layout-versus-schematic process, to verify that it matches theoriginal design specifications for the desired integrated circuit. Ifdiscrepancies between the layout design data 321 and the logical designfor the integrated circuit are identified, then the layout design data321 may be revised to address one or more of these discrepancies. Thus,the layout-versus-schematic process performed by thelayout-versus-schematic module 307 may lead to a new version of thelayout design data with revisions. According to various implementationsof the invention tool 301, the layout data 321 may be manually revisedby a user, automatically revised by the layout-versus-schematic module307, or some combination thereof.

Next, the design rule check module 309 confirms that the verified layoutdata 321 complies with defined geometric design rules. If portions ofthe layout data 321 do not adhere to or otherwise violate the designrules, then the layout data 321 may be modified to ensure that one ormore of these portions complies with the design rules. The design rulecheck process performed by the design rule check module 309 thus alsomay lead to a new version of the layout design data with variousrevisions. Again, with various implementations of the invention tool301, the layout data 321 may be manually modified by a user,automatically modified by the design rule check module 309, or somecombination thereof.

The modified layout data 321 is then processed by the design formanufacturing module 311. As previously noted, a“design-for-manufacture” processes attempts to identify elements in adesign representing structures with a significant likelihood of beingimproperly formed during the manufacturing process. A“design-for-manufacture” process may additionally determine what impactthe improper formation of the identified structures will have on theyield of devices manufactured from the circuit design, and/ormodifications that will reduce the likelihood that the identifiedstructures may be improperly formed during the manufacturing process.For example, a “design-for-manufacture” (DFM) software tool may identifywires that are connected by single vias, determine the yield impactbased upon the probability that each individual single via will beimproperly formed during the manufacturing process, and then identifyareas where redundant visa can be formed to supplement the single vias.

The processed layout data 321 is then passed to the optical proximitycorrection module 313, which corrects the layout data 321 formanufacturing distortions that would otherwise occur during thelithographic patterning. For example, the optical proximity correctionmodule 313 may correct for image distortions, optical proximity effects,photoresist kinetic effects, and etch loading distortions. The layoutdata 321 modified by the optical proximity correction module 313 then isprovided to the optical process rule check module 315

The optical process rule check module 315 (more commonly called theoptical rules check module or ORC module) ensures that the changes madeby the optical proximity correction module 313 are actuallymanufacturable, a “downstream-looking” step for layout verification.This compliments the “upstream-looking” step of the LVS performed by theLVS module 307 and the self-consistency check of the DRC processperformed by the DRC module 309, adding symmetry to the verificationstep. Thus, each of the processes performed by the design formanufacturing process 311, the optical proximity correction module 313,and the optical process rule check module 315 may lead to a new versionof the layout design data with various revisions.

As previously noted, other modules 317 may be employed to performalternate or additional manipulations of the layout data 321, asdesired. For example, some implementations of the tool 301 may employ,for example, a phase shift mask module. As previously discussed, with aphase-shift mask (PSM) analysis (another approach to resolutionenhancement technology (RET)), the geometric elements in a layout designare modified so that the pattern they create on the reticle willintroduce contrast-enhancing interference fringes in the image. The tool301 also may alternately or additionally employ, for example, an etchsimulation analysis processes or a planarization simulation analysisprocesses. The process or processes performed by each of theseadditional modules 317 may also lead to the creation of a new version ofthe layout data 321 that includes revisions.

After all of the desired operations have been performed on the initiallayout data 321, the data export module 319 converts the processedlayout data 321 into manufacturing integrated circuit layout data 323that can be used to form one or more masks or reticules to manufacturethe integrated circuit (that is, the data export module 319 converts theprocessed layout data 321 into a format that can be used in aphotolithographic manufacturing process). Masks and reticles typicallyare made using tools that expose a blank reticle or mask substrate to anelectron or laser beam (or to an array of electron beams or laserbeams), but most mask writing tools are able to only “write” certainkinds of polygons, however, such as right triangles, rectangles or othertrapezoids. Moreover, the sizes of the polygons are limited physicallyby the maximum beam (or beam array) size available to the tool.

Accordingly, the data export module 319 may “fracture” larger geometricelements in the layout design, or geometric elements that are not righttriangles, rectangles or trapezoids (which typically are a majority ofthe geometric elements in a layout design) into the smaller, more basicpolygons that can be written by the mask or reticle writing tool. Ofcourse, the data export module 319 may alternately or additionallyconvert the processed layout data 321 into any desired type of data,such as data for use in a synthesis process (e.g., for creating an entryfor a circuit library), data for use in a place-and-route process, datafor use in calculating parasitic effects, etc. Further, the tool 301 maystore one or more versions of the layout 321 containing differentmodifications, so that a designer can undo undesirable modifications.For example, the hierarchical database 305 may store alternate versionsof the layout data 321 created during any step of the process flowbetween the modules 307-317.

Data Organization

The design of a new integrated circuit may include the interconnectionof millions of transistors, resistors, capacitors, or other electricalstructures into logic circuits, memory circuits, programmable fieldarrays, and other circuit devices. In order to allow a computer to moreeasily create and analyze these large data structures (and to allowhuman users to better understand these data structures), they are oftenhierarchically organized into smaller data structures, typicallyreferred to as “cells.” Thus, for a microprocessor or flash memorydesign, all of the transistors making up a memory circuit for storing asingle bit may be categorized into a single “bit memory” cell. Ratherthan having to enumerate each transistor individually, the group oftransistors making up a single-bit memory circuit can thus collectivelybe referred to and manipulated as a single unit. Similarly, the designdata describing a larger 16-bit memory register circuit can becategorized into a single cell. This higher level “register cell” mightthen include sixteen bit memory cells, together with the design datadescribing other miscellaneous circuitry, such as an input/outputcircuit for transferring data into and out of each of the bit memorycells. Similarly, the design data describing a 128 kB memory array canthen be concisely described as a combination of only 64,000 registercells, together with the design data describing its own miscellaneouscircuitry, such as an input/output circuit for transferring data intoand out of each of the register cells.

By categorizing microcircuit design data into hierarchical cells, largedata structures can be processed more quickly and efficiently. Forexample, a circuit designer typically will analyze a design to ensurethat each circuit feature described in the design complies withspecified design rules. With the above example, instead of having toanalyze each feature in the entire 128 kB memory array, a design rulecheck process can analyze the features in a single bit cell. If thecells are identical, then the results of the check will then beapplicable to all of the single bit cells. Once it has confirmed thatone instance of the single bit cells complies with the design rules, thedesign rule check process then can complete the analysis of a registercell simply by analyzing the features of its additional miscellaneouscircuitry (which may itself be made of up one or more hierarchicalcells). The results of this check will then be applicable to all of theregister cells. Once it has confirmed that one instance of the registercells complies with the design rules, the design rule check softwareapplication can complete the analysis of the entire 128 kB memory arraysimply by analyzing the features of the additional miscellaneouscircuitry in the memory array. Thus, the analysis of a large datastructure can be compressed into the analyses of a relatively smallnumber of cells making up the data structure.

With various examples of the invention, layout design data may includetwo different types of data: “drawn layer” design data and “derivedlayer” design data. The drawn layer data describes geometric elementsthat will be used to form structures in layers of material to producethe integrated circuit. The drawn layer data will usually includepolygons that will be used to form structures in metal layers, diffusionlayers, and polysilicon layers. The derived layers will then includefeatures made up of combinations of drawn layer data and other derivedlayer data. Thus, with a transistor gate, derived layer design datadescribing the gate may be derived from the intersection of a polygon inthe polysilicon material layer and a polygon in the diffusion materiallayer.

For example, a design rule check process performed by the design rulecheck module 309 typically will perform two types of operations: “check”operations that confirm whether design data values comply with specifiedparameters, and “derivation” operations that create derived layer data.A transistor gate design data thus may be created by the followingderivation operation:

gate=diff AND poly

The results of this operation will be a “layer” of data identifying allintersections of diffusion layer polygons with polysilicon layerpolygons. Likewise, a p-type transistor gate, formed by doping thediffusion layer with n-type material, is identified by the followingderivation operation:

pgate=nwell AND gate

The results of this operation then will be another “layer” of dataidentifying all transistor gates (i.e., intersections of diffusion layerpolygons with polysilicon layer polygons) where the polygons in thediffusion layer have been doped with n-type material.

A check operation performed by the design rule check module 309 willthen define a parameter or a parameter range for a data design value.For example, a user may want to ensure that no metal wiring line iswithin a micron of another wiring line. This type of analysis may beperformed by the following check operation:

external metal<1

The results of this operation will identify each polygon in the metallayer design data that are closer than one micron to another polygon inthe metal layer design data.

Also, while the above operation employs drawn layer data, checkoperations may be performed on derived layer data as well. For example,if a user wanted to confirm that no transistor gate is located withinone micron of another gate, the design rule check process might includethe following check operation:

external gate<1

The results of this operation will identify all gate design datarepresenting gates that are positioned less than one micron from anothergate. It should be appreciated, however, that this check operationcannot be performed until a derivation operation identifying the gatesfrom the drawn layer design data has been performed.

Properties

Various implementations of the invention relate to software tools forelectronic design automation that create and/or employ associativeproperties. As will be discussed in more detail below, with someimplementations of the invention, one or more properties can begenerated and associated with any type of design object in a microdevicedesign. If the design is a physical layout for lithographicallymanufacturing an integrated circuit or other microdevice, for example,then one or more properties can be associated with any desired geometricelement described in the design. Referring now to FIG. 4, this figureillustrates a portion of a layout design. The design includes aplurality of polygons 401-407 that will be used to form circuitstructures in a layer of material, such as a layer of metal. Polygons401-405, for example, may be used to form wiring lines for an integratedcircuit. With various examples of the invention, one or more propertiescan be associated with a polygon, such as each of the polygons 401-407,or with a component of a polygon, such as the vertices of a polygon.Further, one or more properties can be associated with a polygon's edge,such as the edge 409 of the polygon 401. Still further, one or moreproperties can be associated with a pair of polygon edges, such as theedges 411 and 413 of the polygon 405. With various examples of theinvention, each property may be represented as a new “layer” of data inthe design.

When a property is associated with a design object in a layout design,its value may be derived from geometric data related to that designobject. For example, if a property is associated with geometric element,such as a polygon, then it may have a value derived from the area of thepolygon, the perimeter of the polygon, the number of vertices of thepolygon, or the like. Similarly, if a property is associated with anedge, then the value of the property may be derived from the length orangle of the edge. Still further, if a property is associated with apair of edges, then the value of the property may be derived from aseparation distance between the edges, a total length of the edges, adifference in length between the edges, an area bounded by the edges,etc.

As will be apparent from the discussion below, however, it should beappreciated that a property value can be defined by any desiredfunction. For example, a property may be defined as a constant value.The value of a property x thus may be defined by the function:

x=0.5

With this definition, the value of the property will always be 0.5.

A property's value also may be defined by a variable function. With avariable function, the value of a property may vary based upon, e.g.,the specific data in the design. For example, a property X may bedefined by the simple function:

x=AREA(METAL1)*0.5+(PERIMETER(METAL1))²

With this function, a property value is generated for every polygon inthe design layer named “metal1.” (That is, the input used to generatethe property X is the data layer in the design name “metal1.”) For eachpolygon in the design layer, the area of the polygon is calculated andmultiplied by 0.5. In addition, the perimeter of the polygon isdetermined, and then squared. The multiplicand of the polygon's areawith 0.5 is then added to the square of the polygon's perimeter togenerate the value of the property X for associated with that polygon.

Thus, in FIG. 4, if the perimeter of the first polygon 401 is 68, andthe area of the first polygon is 64, then the value of the property X ₁for the first polygon is

X ₁=(64*0.5)+(68)²=4656

Similarly, if the perimeter of the second polygon 403 is 60 and the areaof the second polygon is 66, then the value of the property X ₂ of thesecond polygon is

X ₂=(60*0.5)+(66)²=4386.

Still further, if the perimeter of the third polygon 405 is 60 and thearea of the second polygon is 84, then the value of the property X ₃ ofthe third polygon is

X ₁=(60*0.5)+(84)²=7086,

and if the perimeter of the fourth polygon 407 is 34 and the area of thesecond polygon is 70, then the value of the property X ₄ of the fourthpolygon is

X ₄=(34*0.5)+(70)²=4917

In addition to a “simple” function like that described above, a propertyalso may be defined by a compound function that incorporates apreviously-generated property value. For example, a first property x maybe defined by the simple function described above:

X=AREA(METAL1)*5+(PERIMETER(METAL1))²

A second property, Y, can then be defined by a function thatincorporates the value of the first property X, as follows:

Y=PROP(METAL1,X)+1

Thus, the value of the property Y for a polygon is the value of theproperty x calculated for that polygon, plus one.

In addition to being defined by simple and compound functions, aproperty may be defined so that no property value is generated undersome conditions. For example, a property associated with a polygon maybe defined so that, if the area of the polygon is smaller than athreshold value, then no value is generated for the property. Thisfeature may be useful where, for example, property values need only begenerated for design objects having desired characteristics. If a designobject does not have the required characteristics, then no property willbe generated for the design object and it can be ignored in subsequentcalculations using the generated property values.

More generally, a property's value may be defined by alternativefunctions, such as the functions below:

IF AREA(METAL1)<0.5, THEN X=1

IF AREA(METAL1)≧1, THEN X=AREA(METAL1)*0.5+(PERIMETER(METAL1))²

With these alternative functions, each polygon in the data layer“metal1” is analyzed. If the area of the polygon is below 0.5, then thevalue of the property X for the polygon is 1. Otherwise, the value ofthe property X for the polygon is the area of the polygon multiplied by0.5, added to the square of the perimeter of the polygon.

A property may have multiple values. For example, a property may have anx-coordinate value, a y-coordinate value, and a z-coordinate value.Moreover, a property may have multiple, heterogeneous values. Forexample, a property may have a numerical value and a string value. Thus,a property associated with a cell can have a numerical value that maybe, e.g., a device count of devices in the cell, while the string valuemay be, e.g., a model name identifying the library source for the cell.Of course, a property with multiple heterogeneous values can include anycombination of value types, including any combination of the value typesdescribed above (e.g., one or more constant values, one or more vectorvalues, one or more dynamic values, one or more alternate values, one ormore simple values, one or more compound values, one or more alternatevalues, one or more string values, etc.).

Still further, the number of values of a property may change dynamicallychange. For example, a property K may have the values “a” and “b” (i.e.,value of property K=a, b) before an electronic design automation processis executed. The electronic design automation process may then changethe property to include a third value “c” (i.e., value of property K=a,b, c). Of course, the electronic design automation process also mayalternately or additionally change the values of property K to one ormore completely different values (e.g., value of property K=d, e, f).Moreover, with some implementations of the invention, the value of aproperty at one time may depend upon the value of the property at aprevious time. For example, the value of a property Q at time t₂ may bederived from the value of the property Q at time t₁. Of course, inaddition to constant values, and values generated based upon simple,compound, or alternative variable functions, a property's value can bespecified according to any desired definition. For example, in additionto single or alternate mathematical functions, the value of a propertymay even be an array of constant values, variable functions, or somecombination thereof. It should be appreciated, however, that, by using ascripting language as described above, property values can bedynamically generated during an electronic design automation process.

That is, by specifying property value definitions using a scriptinglanguage, the actual property values can be generated based upon thedefinitions when the design is analyzed during an electronic designautomation process. If the data in the design is changed, then theproperty values will automatically be recalculated without requiringfurther input from the designer. Thus, employing a scripting languageallows a designer or other user to develop properties and determinetheir values as needed. It also may provide the flexibility to allowthird parties to develop new analysis techniques and methods, and thenspecify scripts that allow the user of an electronic design automationtool to use the scripts developed by a third party to generate propertyvalues for use with those new techniques and methods.

As previously noted, a property may be associated with any desired typeof design object in a design. Thus, in addition to a single geometricelement in a layout design, such as a polygon, edge, or edge pair, aproperty also can be associated with a group of one or more designobjects in a layout design. For example, a property may be associatedwith a group of polygons or a hierarchical cell in a layout design(which themselves may be considered together as a single design object).A property also may be associated with an entire category of one or moredesign objects. For example, a property may be associated with everyoccurrence of a type of design object in a design layer, such as withevery cell in a design, or every instance of a type of geometric elementoccurring in a design. A property also may be specifically associatedwith a particular placement of a cell in a design. In addition to designobjects in a layout design, properties also may be associated withdesign objects in other types of designs, such as logical designs. Aproperty thus may be associated with any desired object in a logicaldesign, such as a net, a device, an instance of a connection pin, oreven a placement of a cell in the design.

It also should be appreciated that, with various embodiments of theinvention, a property associated with one design object also can beassociated with another design object. Further, a property's value maybe calculated using geometric or logical data for any desired designobject, including design objects different from the design object withwhich the property is associated. With some implementations of theinvention, a property's value may even be calculated using geometric orlogical data for one or more design objects from multiple design datalayers. For example, a designer may specify a design layer entitled“pair” that includes any specified edge pairs in a layout design, andanother design layer entitled “edge” that includes specified edges in alayout design. A designer can then define a property z for each edge inthe edge layer as:

Z=AREA(METAL1)/LENGTH(EDGE)+EW(PAIR)

where AREA is the area of one or more polygons related to the edge,LENGTH is the length of the edge, and EW is the width between the edgesof an edge pair related to the edge. Thus, the value of the property Zfor an edge is dependent upon the area of some other polygon related tothe edge.

With some implementations of the invention, various algorithms can beused to define which design objects, such as geometric elements, will berelated to each other for use in a property definition. For example, thedefinition for property z above may employ a relationship algorithm thatincludes a polygon in the property value determination if the polygontouches the edge associated with the property, and includes an edge pairin the property value determination if one edge is the edge associatedwith the property and the second edge is connected to the first edgethrough a polygon (i.e., both edges are part of the same polygon, asopposed to being separated by an empty space).

Of course, any desired algorithms can be used to determine which designobjects will be related to each other for determining the value of aproperty. Other possible relationship algorithms for physical layoutdesigns, for example, may relate all geometric elements that overlap,all geometric elements that intersect, all geometric elements that touchor otherwise contact each other, or all geometric elements that arewithin a defined proximity of another geometric element. With stillother relationship algorithms, if one geometric element touches multiplegeometric elements, the algorithms can decide to treat the touchinggeometric elements as errors, or to relate all touched shapes. Stillother relationship algorithms can employ clipping, where, e.g., if afirst geometric element intersects a second geometric element, only thepart of the second geometric element inside the first geometric elementis employed when determining a property value, etc.

Similarly, a variety of relationship algorithms can be used to relatedesign objects in a logical design to each other for use in a propertydefinition. For example, a property definition may relate all designobjects that belong to the same logical device, all design objects thatshare a common net, or all design objects that share a referenceidentifier with, e.g., the design object with which the property isassociated. Of course, still other relationship criteria can be employedto relate design objects in designs to each other for use in a propertydefinition.

Further, by defining a second property value so that it incorporates afirst property value, a property value associated with any design objector group of design objects can be associated with any other designobject or group of design objects. For example, a property for a firstpolygon may be the area of that polygon. A property for a second polygontouching or contacting that first polygon can then be defined as thearea of the first polygon. In this manner, a property value associatedwith the first polygon can be associated with the second polygon. Thus,a property associated with a geometric element also can be associatedwith a cell incorporating that geometric element. Similarly, a propertyassociated with a geometric element can be associated with an adjacentgeometric element. Still further, a property of a geometric element canbe associated with the entire data layer in a design.

With various implementations of the invention, the value of a propertyassociated with a design object property value is separate from adescription of the design object with which the property is associated.That is, with various implementations of the invention the value of aproperty is not simply a characteristic of the design object with whichthe property is associated, but instead may be considered a distinctdesign object itself. According to some implementations of theinvention, for example, the property values for various design objectsmay be stored in an array. FIG. 5 illustrates one example of a type ofarray that may be employed by various implementations of the invention.As seen in this figure, the array 501 includes a column listingidentifiers 503. It also includes a column with property values 505 fora property G, a column with property values 505 for a property H, and acolumn with property values 505 for a property I.

Each identifier 503 identifies an occurrence of a design objectassociated with each of the properties G, H, and I. With the illustratedexample, the design object may be, e.g., a type of cell in ahierarchical physical layout design. The definition for the property Gthen may be the coordinate value for the placement of the cell, whilethe definition of the property H may be both the library from which thecell was obtained and the count of the cell in the design. Thedefinition of the property I then may be the percentage at which thestructure described in the cell will be improperly formed during amanufacturing process. From the array 501, it can thus be determinedthat, e.g., the cell “design object 8” is located at the x, y coordinatevalues 40, 8 in the design, was originally obtained from library 8, andis the ninth occurrence of that cell in the design. Also, the value ofproperty I for this cell indicates that it has a 0.000009% failure ratewhen manufactured.

While a table-type array is illustrated in FIG. 5 for each ofunderstanding, it should be appreciated that, as used herein, the term“array” is intended to encompass any type of data structure that behaveslike a logical array. Thus, various implementations of the invention mayalternately or additionally employ, for example, such structures as aCalibre number table (used with the Calibre family of software toolsavailable from Mentor Graphics Corporation of Wilsonville, Oreg.) or aStandard Template Library (STL) deque. It also should be appreciatedthat, while FIG. 5 illustrates a single set of property values for eachdesign object, various implementations of the invention may allowmultiple identifies to be associated with a single set of propertyvalues. This arrangement may be beneficial, e.g., for reducing memoryusage where one or more design objects will have the same value for anassociated property. Also, it should be noted that variousimplementations of the invention may update a property value byoverwriting or otherwise replacing the previous property value in memorywith the updated property value, to conserve memory usage.

Transfer of Property Values From One EDA Process to Another EDA Process

One use of properties according to various implementations of theinvention is to transfer information determined in one electronic designautomation process to another electronic design automation process in aformat that can readily be used by the second electronic designautomation process. For example, properties can be defined and used totransfer information from a simulation analysis process (such as anoptical proximity correction process, an etch simulation analysisprocess, or a planarization simulation analysis process) to a geometryanalysis process (such as a design rule check process, a design formanufacturing process, or an optical rules check process) or a logicanalysis process (such as a layout-versus-schematic process, anelectrical rule checking process, or a design logic verificationprocess). Similarly, properties can be used to transfer information froma geometry analysis process to a simulation analysis process or a logicanalysis process, or to transfer information from a logic analysisprocess to a simulation analysis process or a geometry analysis process.

A variety of information can be transferred from one EDA process toanother EDA process. For example, one EDA process could, in the courseof operation, determine information relating to the yield of designobjects in a layout design, and provide that information as propertyvalues associated with the design objects. Yield information mayinclude, for example, the likelihood that a design design object willnot be manufactured correctly and thus will not perform according tospecification.

For example, referring back to FIG. 4, the likelihood that two adjacentparallel wiring lines will be improperly manufactured and “bridge”together may be dependent upon the width of the lines, the distancebetween the lines, and the length for which the lines are adjacent. Asdiscussed in detail above, the value of a property Z can take intoaccount the area of one or more polygons related to the edge 411, thelength of the edge 411, and the width between the edges 409 and 411.Accordingly, the value of this property (or a property with a similardefinition that relates these features) can be used to determine thelikelihood that the wires 409 and 411 will bridge together during amanufacturing process. Thus, an EDA process that can easily calculatethe value of property Z, such as a design-rule-check process, candetermine a value for the property Z with respect to the line 409 or theline 411. Anther EDA process, such as a DFM process, can then employthat property value to, e.g., determine the likelihood that the wires409 and 411 will bridge together during a manufacturing process

Still other information that may be generated during one EDA process andthen provided to another EDA process is failure prediction. Failureprediction may, e.g., map yield information to particular designfeatures. For example, if a via has a low yield, and if its failure willcause a device in the manufactured circuit to be “stuck open,” thefailure prediction information may correlate the low yield of the via tothe likelihood that a net connected to the device will be stuck open.Still other information that may be generated during one EDA process andthen provided to another EDA process as property information includestest hints, which suggest test patterns to stress potential failure in amanufactured circuit. For example, the test hint may suggest testpatterns that will test potential failures identified by failureprediction information. It also may include reliability information,corresponding to delayed failures that may occur during the use of themanufactured device, such as the failure of a contact from thermalstress. Yet other information that can be conveyed from one EDA processto another EDA process as property information includes reliability andmanufacturability metrics. These metrics may be, e.g., specificqualitative characteristics for certain failure mechanisms such as, forexample, variation across process window or probability of photoresistcollapse.

Additionally, planarity information can be conveyed from one EDA process(such as a planarization simulation analysis process) to another EDAprocess. This type of information may include, e.g., informationgenerated using planarity models that simulate the process ofchemical-mechanical polishing to predicted thickness after polishingbased on distribution of hardness of the materials across the chip(oxide is harder than everything else, copper is softer, polysilicon isin between). Still further, heat dissipation information may bedetermined by one EDA process, and then provided to anther EDA processin the form of property values.

FIG. 6 illustrates a flowchart showing a method that an EDA process mayuse to generate and provide a property value to another EDA process. Instep 601, the first EDA process receives design data. Next, in step 603,the first EDA process analyzes the design data, and in step 605generates one or more property values from the design data based uponthe definition of the property. The, in step 607, the first EDA processstores the property values in a memory storage medium for use by thesecond EDA process. With various implementations of the invention, thememory storage medium may be any type of storage medium, such as aprocessor register, RAM, a magnetic memory storage disc, an opticalstorage disc or other format, etc. In step 609, the second EDA processobtains the stored property values for use in its own execution. Withsome implementations of the invention, the generated property values maybe provided immediately to the second EDA process. With thisarrangement, the property values may only be briefly stored in memory,such as in a process register. For still other implementations, however,the property values may be stored in a more long-term storage medium,and the second EDA process initiated some time after the property valueshave been generated.

Transfer of Property Values from an OPC Process to a DFM or LVS Process

To illustrate one example of the exchange of properties between EDAprocess in more detail, the use of properties to transfer informationfrom an OPC process to a DFM process or to an LVS process will bediscussed. Optical proximity correction (OPC) is one type of processfrequently provided by electronic design automation tools. Asmicrocircuits have evolved to include smaller and smaller features, manycircuit designs now include features that are smaller than the lightwavelength that will be used to create those features during alithographic process. This type of subwavelength imaging often createsdistortions during the lithographic process, however. To address thesedistortions, correction algorithms are employed to modify the physicallayout of the circuit design, as noted above. This process is generallycalled optical proximity correction (OPC). Thus, as used herein, theterm optical proximity correction includes the modification of aphysical layout of a circuit design to improve the reproduction accuracyof the layout during a lithographic process. In addition, however, theterm optical proximity correction as used herein will also include themodification of the physical layout design to improve the robustness ofthe lithographic process for, e.g., printing isolated features and/orfeatures at abrupt proximity transitions.

During optical proximity correction, the polygon edges of the physicallayout are divided into small fragments. These fragments are then moved,and additional small polygons may be added to the physical layout atstrategic locations. The lithographic process is then simulated todetermine whether the image that would be created by the modified or“corrected” layout would be better than the image created that would becreated by previous modifications to the layout image. This process isthen iteratively repeated until a modified layout the simulation andverification tool generates a modified layout that will produce asatisfactory image resolution during an actual lithographic process.

Typically, optical proximity correction techniques are classified aseither rule-based or model-based. With rule-based optical proximitycorrection, the layout modifications are generated based upon specificrules. For example, small serifs may be automatically added to eachconvex (i.e., outwardly-pointing) 90° corner in the layout. Model-basedoptical proximity correction generally will be significantly morecomplex than rule-based optical proximity correction. With model-basedoptical proximity correction, lithographic process data obtained fromtest layouts are used to create mathematical models of the lithographicpatterning behavior. Using an appropriate model, the simulation andverification tool will then calculate the image that will be created bya corrected layout during the lithographic process. The layout featuresundergoing correction then are iteratively manipulated until the imagefor the layout (calculated using the model) is sufficiently close to thedesired layout image. Thus, some model-based optical proximitycorrection algorithms may require the simulation of multiplelithographic process effects by a calculating a weighted sum ofpre-simulated results for edges and corners. An example of an opticalproximity correction algorithm is described in “Fast Optical Process AndProximity Correction Algorithms for Integrated Circuit Manufacturing,”by Nick Cobb (Ph.D. Thesis), University of California, Berkeley, 1998.

As will be appreciated by those of ordinary skill in the art, performinga rule-based optical proximity correction process is computationallymore intensive than performing a design rule check, and performing amodel-based optical proximity correction is even more so. Further, thecomputations required for the optical proximity correction process aremore sophisticated than the computations that usually would be employedin a design rule check process. Obtaining a simulated lithographicimage, for example, may involve modeling the lithographic light sourceas a plurality of separate coherent light sources arranged at differentangles. For each such coherent light source, a simulated image isobtained by calculating a fast Fourier transform (FFT) to model theoperation of the lens used in the lithographic process. These simulatedimages are then summed to obtain the image that would be produced by thelithographic process.

Accordingly, an OPC process will employ a different data “resolution”than a DFM or LVS process. For example, in analyzing a simplerectangular polygon that represents a transistor gate, the OPC processmay transform the rectangular polygon into a contoured polygon withperhaps millions of edges. Thus, an OPC process will typically executemassively parallel operations that (1) divide relatively large polygonsin a design into a much larger number (e.g., a million) of relativelysmall polygons, and (2) may require ignoring a hierarchical structure ofthe data being analyzed. As a result, information generated by an OPCprocess typically is incompatible with a DFM or LVS process, each ofwhich usually executes calculations on the relatively large polygons inthe original design, and significantly benefits from performing thosecalculations using a hierarchical arrangement in the design.

For example, with a rectangular polygon representing a transistor gate,an OPC process will generate a very contoured polygon that representsthe actual details of the gate's shape after diffraction has occurred ina lithographic manufacturing process. An LVS process, on the other hand,only requires an overall width and length of the gate to characterizethe device. Accordingly, an LVS process may use a formula that averagesthe widths of the contoured gate shape calculated by the OPC process,and this average value is then used by the LVS to characterize thedevice. In order to calculate this average width value, however, the LVSprocess typically must obtain the detailed contour information from theOPC process, which is undesirable. With various examples of theinvention, these average width values can easily be calculated by theOPC, and the results attached as property values to the original gatepolygon. These property values describing contour information, whichwere efficiently calculated by the OPC process, then can be passed ontothe LVS process. In turn, the LVS process can then be configured to usethe received property values to identify the device. In this manner,each process can operate in its optimum mode for processing design data.

As will be appreciated by those of ordinary skill in the art, thetransfer of information from an OPC process to a DFM process viaproperties is similar, but can more generic, in that a broad range ofinformation may be analyzed in a DFM process. For example, a DFM processmay wish to perform a fault probability calculation for a wire basedupon a “pullback” value for a wire (an amount that the wire will retractor extend due to diffraction in a manufacturing process). Typically, aDFM process cannot easily calculate this type of value. With variousexamples of the invention, however, an OPC process can calculate apullback value for a wire, and then attach this value as a propertyvalue to the simple layout polygon on which the OPC analysis wasperformed. A DFM process can then subsequently use this pullback valueto improve the accuracy of the DFM process results without requiring acorresponding increase in calculations.

In addition to pullback information, an OPC process may determine stillother types of contour information as one or more property values, andpass those property values onto an LVS or DFM process. For example, theOPC process may generate property values describing gate variation,contact stability, interconnection variation, bridging, etc. By thenproviding these property values to an LVS or DFM process, the LVS or DFMprocess can then use these values during its own operation, withouthaving to recalculate the information.

Yet another example of the use of properties to transfer informationfrom one electronic design automation process to another electronicdesign automation process relates to the determination of a variationband. Process variation bands are discussed in detail in U.S. PatentPublication No. 20050251771, published on Nov. 10, 2005, entitled“Integrated Circuit Layout Design Methodology With Process VariationBands,” naming Juan Andres Torres Robles as inventor, which publicationis incorporated entirely herein by reference. A process variation bandcan be calculated by an OPC process. The process variation bandrepresents a range of possible shape variations produced by a polygon ina layout design that may result from diffraction created by differentprocess conditions during a manufacturing process. The results of theprocess variation band can then be attached to the corresponding polygonfor subsequent use in a DFM process. For example, a polygon may haveassociated property values that can include both calculated geometricvalues (e.g., a band deviation of 0.1) and parameters at which thosegeometric values were calculated (e.g., the band deviation of 0.1 wascalculated for a defocusing of 1%).

This property information provided by the OPC process then can be usedby a DFM process in any desired manner. For example, a DFM can do aninitial check for bridging faults using the simple polygons in theoriginal layout design. Where the DFM process determines that there is alikelihood of a fault, the DFM process can check the process variationband values provided as associated property values to calculate if afault will occur (or the likelihood that a fault may occur) with greateraccuracy. Still further, the DFM process can alternately or additionallydetermine a failure area falling between two adjacent “marker” areas onadjacent lines. Using the process variation information passed asproperty values from the OPC process, the DFM process then can determinea process variation index that represents the overlap of the processvariation band area with the fault area (as, e.g., a simple ratio).Based upon this process variation index, the DFM process can determinethe likelihood of a fault occurring at the associated bridge area. Byadding up the process variation index values (which themselves can berecorded as property values) for each marker in a wire, the DFM valuecan, e.g., identify the wire in a design that is most likely to cause afault, or identify a marker area that is most likely to cause wire tofail, etc.

As discussed above, various examples of the invention have beendescribed with regard to the use of property values generated during anOPC process in subsequent electronic design automation processes. Itshould be appreciated, however, that the use of property values are notlimited to those generated during an OPC process. Other implementationsof the invention may, for example, use property values generated by anyoptical-related electronic design automation process in other,subsequent electronic design automation processes. For example, someimplementations of the invention may similarly use property valuesgenerated during an optical proximity rule check (ORC) process or aphase shift mask (PSM) process in subsequent electronic designautomation processes.

Transfer of Property Values Between a DFM Process and an LVS Process

Still further, properties may be employed according to various examplesof the invention to transfer information from a DFM process to a LVSprocess. An LVS process typically identifies or characterizes a deviceby starting with a basic polygon in the device as the source of a deviceidentification, and then analyzing each touching or overlapping polygonin the design to determine the extent of the device. As a result, a LVSprocess typically cannot consider polygons that are separate from adevice as part of the device's identification analysis. In order toaccurately characterize a device in a design, however, an LVS processmay need to use of measurements of geometric features that are outsideof what the LVS process would normally recognize as being related to thedevice.

For example, in order to characterize the operation of a device usingstrained silicon, such as a transistor, the LVS process may the amountof stress applied to the transistor gate by the strained silicon. Inorder to make this determination, the LVS process should know a distancebetween the strained silicon material and any holes formed in anadjacent but separate device (e.g., a wire). Because the LVS processcannot measure features relating to the adjacent device, however, it maynot be able to accurately characterize the strained silicon device. Withvarious examples of the invention, however, a DFM process can measuredistances between the strained silicon device and holes in an adjacentwire. The DFM process then can record these measurements as propertyvalues associated with polygon representing the gate of the strainedsilicon device. The LVS process can then subsequently employ theseproperties to characterize the operation of the strained silicon devicewithout having to perform any analysis of adjacent devices. Accordingly,it may be useful for an LVS process to have some information outside ofa device's boundaries, and this external information can be provided tothe LVS process by another process using property values in accordancewith various implementations of the invention.

Still further, property values can be passed from an LVS process to aDFM process. For example, an LVS process can identify polygons in adesign that represent gates for a high-current MOS transistor, and thenrecord property values for these polygons identifying them as gates fora high current MOS transistor (e.g., as a property with a numericalvalue of a current load for the gate identifying it as a high currentMOS, or as a property with a string value of “high current MOS,” etc.).These property values then can be passed back to the DFM process. TheDFM process could then use a filter to identify the high-current MOSstructures, and perform whatever operation is desired on thosestructures identified through the filter.

Still further, properties can be used to transfer information from adesign object in one type of design to another design object in anothertype of design. For example, an LVS process can determine operationalcharacteristics for a design object in a design, such as the capacitanceof a transistor. The LVS process can then store these operationcharacteristics as property values associated with the data structure,and provide these property values to a corresponding data structure in,e.g., a logical design. Similarly, a DFM process may use a PEX(parasitic extraction) process to calculate, e.g., capacitance, whichcan then be employed as a property in a layout design or a schematicdesign.

Transfer of Properties within an EDA Process

Another use of properties that may be employed according to variousimplementations of the invention is to transfer information from oneportion of an electronic design automation process to another portion ofthat electronic design automation process in a format that can readilybe used by the second portion of the electronic design automationprocess. Again, a variety of information can be transferred within asingle EDA process using property values, such as yield information,failure prediction information, and test hints. It also may includereliability information, reliability and manufacturability metrics,planarity information, and heat dissipation information.

FIG. 7 illustrates a flowchart showing a method that a first portion ofan EDA process may use to generate and provide a property value to asecond portion of the EDA process. In step 701, the first portion of theEDA process receives design data. Next, in step 703, the first portionof the EDA process analyzes the design data, and in step 705 generatesone or more property values from the design data based upon thedefinition of the property. The, in step 707, the first portion of theEDA process stores the property values in a memory storage medium foruse by the second portion of the EDA process. With variousimplementations of the invention, the memory storage medium may be anytype of storage medium, such as a processor register, RAM, a magneticmemory storage disc, an optical storage disc or other format, etc. Instep 709, the second portion of the EDA process obtains the storedproperty values for use in its own execution. With some implementationsof the invention, the generated property values may be providedimmediately to the second portion of the EDA process. With thisarrangement, the property values may only be briefly stored in memory,such as in a process register. For still other implementations, however,the property values may be stored in a more long-term storage medium,and the second portion of the EDA process initiated some time after theproperty values have been generated.

Transfer of Properties within a DFM Process

Again, to illustrate one example of the exchange of properties within asingle EDA process in more detail, the use of properties to transferinformation within a DFM process will be discussed. Different functionsof a DFM process can use different levels of data “resolution.” A DFMprocess may provide a high level manufacturing yield calculation for anentire circuit, which will have a different data resolution than a faultprobability using detailed information for a specific combination ofgeometric elements. Accordingly, a DFM process will calculate faultinformation for individual geometric elements, and attach this faultinformation as property values to a higher level design object (e.g., anet or a cell) for use when a designer wishes to perform a broaderanalysis of yield probabilities.

Moreover, a DFM process can calculate enhancements, such as doubled viasto avoid via formation failures. With via doubling, for example, asecond via can be placed at one of four possible locations relative tothe original via (i.e., above, below, to the left, or to the right). ADFM process could calculate all possible options, determinecharacteristics for each option (e.g., capacitance change) for eachoption, and save the determined characteristics as property values.Various option combinations could then be generated using the propertiesto determine an optimum option selection that would comply with desiredspecifications. The property values also could be used to determine apotential loss with each element based upon process parameters, and todetermine how much a process improvement would result in a yieldimprovement.

CONCLUSION

While the invention has been described with respect to specific examplesincluding presently preferred modes of carrying out the invention, thoseskilled in the art will appreciate that there are numerous variationsand permutations of the above described systems and techniques that fallwithin the spirit and scope of the invention as set forth in theappended claims. For example, while specific terminology has beenemployed above to refer to electronic design automation processes, itshould be appreciated that various examples of the invention may beimplemented using any desired combination of electronic designautomation processes.

Thus, in addition to use with “design-for-manufacture” processes,various examples of the invention can be employed with“design-for-yield” (DFY) electronic design automation processes, “yieldassistance” electronic design automation processes,“lithographic-friendly-design” (LFD) electronic design automationprocesses, including “chip cleaning” and “design cleaning” electronicdesign automation processes, etc. Likewise, in addition to use with“design-rule-check” electronic design automation processes, variousimplementations of the invention may be employed with “physicalverification” electronic design automation processes. Also, in additionto being used with OPC and ORC electronic design automation processes,various implementations of the invention may be used with any type ofresolution enhancement electronic design automation processes.

1. A method of analyzing a circuit design, comprising: receiving acircuit design at an electronic design automation process; executing afirst portion of the electronic design automation process; during theexecution of the first portion of the electronic design automationprocess, determining a value for a property associated with a designobject in the circuit design; and storing the property value in a memorystorage medium for use by a second portion of the electronic designautomation process.
 2. The method recited in claim 1, further comprisingexecuting the second portion of the electronic design automation processusing the property value.
 3. The method recited in claim 2, furthercomprising manufacturing a circuit based upon results of executing thesecond portion of the electronic design automation process using theproperty value.
 4. The method recited in claim 1, wherein the electronicdesign automation process is selected from the group consisting of: ageometry analysis process, a simulation analysis process, and a logicanalysis process.
 5. The method recited in claim 4, wherein theelectronic design automation process is a geometry analysis processselected from the group consisting of: a design for manufacturingprocess and a design rule check process.
 6. The method recited in claim4, wherein the electronic design automation process is a simulationanalysis process selected from the group consisting of: an opticalproximity correction process, an etch simulation analysis process, and aplanarization simulation analysis process.
 7. The method recited inclaim 6, wherein the simulation analysis process is an optical proximitycorrection process, and further comprising determining the propertyvalue to describe information derived by the optical proximitycorrection process selected from the group consisting of: contourinformation, pullback information, pinching information, bridginginformation, gate variation information, contact stability information,and interconnect variation information.
 8. The method recited in claim6, wherein the simulation analysis process is an optical proximitycorrection process, and further comprising determining the propertyvalue to describe a process variation band derived by the opticalproximity correction process related to the design object with which theproperty is associated.
 9. The method recited in claim 4, wherein theelectronic design automation process is a logic analysis process. 10.The method recited in claim 9, wherein the logic analysis process isselected from the group consisting of: a layout-versus-schematicprocess, an electrical rule checking process, and a design logicverification process.
 11. The method recited in claim 9, wherein thelogic analysis process is a layout-versus-schematic process, and theproperty value is related to operational characteristics of anelectronic device represented by the design object with which theproperty is associated.